1. Field
The following description relates to a semiconductor power device and a method of fabricating the same, and to, for example, a semiconductor power device with at least one buried layer and a method of fabricating the same without a high-energy ion implantation process, the buried layer being formed by adding one or more epitaxial layers in a high-voltage lateral DMOS (LDMOS).
2. Description of Related Art
MOSFET devices with high-switching frequency and low power loss have been widely used in power conversion and regulation circuits. There are multiple types of Power MOSFET devices that are referred to as double-diffused DMOS transistors. For example, there is a vertical version of a DMOS transistor, known as vertical double-diffused metal oxide semiconductor (VDMOS). Also, there is a lateral version of a DMOS transistor, known as lateral double-diffused metal oxide semiconductor (LDMOS).
When a silicon-on-insulator (SOI) substrate is used to fabricate a power integrated circuit (power IC), the manufacturing process may be simplified as compared to that used with a bulk silicon substrate. However, the cost of SOI substrates is too high for the practical application of such a manufacturing process for most purposes.
VDMOS transistors have large power handling capabilities. However, VDMOS transistors are more difficult to realize in an IC technology in comparison to LDMOS transistors. Thus, LDMOS devices are widely used as a switch for control, logic, and power. LDMOS devices require a high breakdown voltage to endure a high applied voltage. At the same time, these devices require low on-resistance to minimize conduction losses.
A reduced surface field (RESURF) structure, which reduces the peak electric field in the drain region of MOSFETs to obtain a high breakdown voltage and low on-resistance simultaneously, has been developed in the early 1980's. However, in the RESURF processing of conventional art, a high-energy ion implantation process of typically greater than 1 MeV is needed to form the P type buried layer in order to achieve a depth that is sufficient to form the first conduction path. In addition, in the event that additional P type buried layers have to be formed to further reduce the resistance, even higher ion-implantation energy is necessary to form the additional P type buried layers. For instance, an implantation process involving greater than 2 MeV may be necessary, which may not be feasible in many device fabrication facilities.